1. Field of the Invention
The present invention relates to a process for manufacturing power MOS lateral transistors.
More specifically, the invention relates to a process for manufacturing shielded power MOS lateral transistors together with VLSI CMOS devices, on a same semiconductor substrate which comprises a semiconductor region of a first type of conductivity, the process comprising the following steps of:                forming, on said semiconductor region, at least one lateral MOS transistor which comprises a gate electrode projecting from said semiconductor region and being insulated therefrom by means of an insulating layer, a source region comprising a first highly doped portion of a second type of conductivity aligned with said gate electrode and a realized drain region comprising a first lightly doped portion aligned with said gate electrode and a second highly doped portion included in said first lightly doped portion, both of the second type of conductivity.        
The invention particularly, but not exclusively, relates to a process for manufacturing shielded power MOS lateral transistors in VLSI CMOS technology and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, high efficiency power discrete MOSFET lateral transistors integrated on a silicon semiconductor substrate are realized, for example, by means of MOSFET transistors of the drain extension or LDMOSFET (lateral double diffused MOSFET) type.
As shown in FIG. 1, an N-channel MOS transistor DE of the conventional drain extension type integrated on a semiconductor substrate having a semiconductor region 1a of the P type, wherein a body region 2a of the P type is realized, which is more doped than a semiconductor region 1a adjacent to a drift region 3a of the N− type.
Inside the body region 2a, a first implanted region 4a of the P+ type, being more doped than the adjacent body region 2a, and a second implanted region 5a of the N+ type are realized. In particular, such implanted regions 4a and 5a do not contact the drift region 3a and they realize the transistor DE source region.
Inside the drift region 3a, a third implanted region 6a of the N+ type is realized. In particular, the third implanted region 6a does not contact the body region 2a and it realizes, together with the drift region 3a, the transistor DE drain region.
On the semiconductor region 1a, between the drift region 3a and the second region 5a, a gate electrode 8a is realized, which is insulated from the semiconductor region 1a by means of an oxide layer 7a. 
The gate electrode 8a comprises a polysilicon layer 9a overlapped by a silicide layer 10a. Dielectric spacers 11a are also provided on the side walls of the gate electrode 8a. 
Once a premetal dielectric layer 12a has been formed on the whole device DE, contacts 13a and 14a are conventionally formed at the respective source and drain regions.
Recently, the need of reducing the feedback gate-drain capacitance Cgd of such discrete LDMOSFET devices is felt, improving at the same time the reliability thanks to the reduction of the hot carriers phenomenon. Such feedback gate-drain capacitance Cgd is generally made of three components: C1 due to the capacitance between the gate electrode and the drift region portion geometrically underlying the gate electrode, C2 due to the capacitance between the gate electrode and the portion of the drift region lying outside the gate electrode, and C3 due to the capacitance between the gate electrode and the drain metallic contact.
Moreover, it is known that the reduction of the MOSFET feedback capacitance allows to increase the high frequency gain, to improve the amplification unilaterally and to decrease the signal distortion. This advantage is particularly important in the radiofrequency power amplifiers for wireless applications, where, often, RF LDMOSFET transistors are used as amplification elements.
It is also known that a shielding electrode, in general connected to the source region, suitably placed between the drain region and the gate electrode, reduces such feedback capacitance, in particular its components C2 and C3. Its “field plate” effect, moreover, allows to reduce the electrical fields at the edge of the polysilicon layer forming the gate electrode towards the drain region, reducing the hot carriers phenomenon which could affect the component reliability.
A first solution to manufacture such a shielding electrode in a MOSFET device of the discrete type, is described in the international application no. WO 0111681 to Spectrian Inc.
In such device, as shown in FIG. 2, after having realized the doped regions 14, 16, 25 and 28 in the substrate 10 and the gate electrode 22 in the substrate 10, 12, a first dielectric layer 24 and a second dielectric layer 30 are deposited on the whole device. Thus, a first opening is realized in the second dielectric layer between the gate electrode and the drain region to realize the shield electrode 34. Subsequently, two openings are realized both in the first and in the second dielectric layer in correspondence with the source and drain terminals to realize the source and drain contacts 36, 38.
Although advantageous under several aspects, this solution is not compatible with the processes for realizing the VLSI CMOS transistors. In fact, the formation of the dedicated dielectric layer 24 to realize the shield 34, the realization of the openings in sequence in the premetal dielectric layers and the use of layers of different metalizations for the shield on one side and contacts on the other, is expensive and not simple to be realized during the standard procedures of the VLSI CMOS devices, especially in case shielded lateral MOSFET devices of reduced sizes are realized with VLSI technology. The presence of these additional technological steps could also introduce undesired electrical variations in the realized final VLSI CMOS devices.
A second solution, which provides to realize the shield metalization by means of the metalization layer forming the source metalization, with subsequent simplification and saving of a mask with respect to the previous solution, is described in the U.S. Pat. No. 6,744,117 to Motorola Inc.
In particular, as shown in FIG. 3, after having realized the source 19 and drain 20 regions and the sinker region 21 in the substrate 11 and the gate electrode 15 on such substrate 11, an intermetal dielectric layer 23 is deposited, wherein openings are realized on the source 19 and drain 20 regions. A metallic layer is formed on the device to form a metallic shield 27, the first drain contact 26 and a bus 29.
Although meeting the aim, even this solution is not exempt from drawbacks.
The efficiency of the shielding and “field plate” effect of the metallic shield 27 however depends on the proximity of the same with respect to the drain region 20. A decrease of the thickness of the intermetal dielectric layer 23 to improve the shield efficiency would inevitably imply a capacitance increase of the metalization layer towards the gate electrode 15 with subsequent reduction of the device cut-off frequency. Then, in case one would like to use a similar approach in a VLSI CMOS platform where the premetal and intermetal dielectrics are perfectly planarized the shielding effect of the metalization layer would be lost due to the great distance of the metallic shield 27 from the substrate 11.
To overcome some of these drawbacks, it is proposed to realize a polysilicon shield as described in the U.S. Pat. Nos. 6,107,160 and 6,172,400 to Spectrian Corporation.
However, in the VLSI CMOS platforms, or more in general for high performance MOSFET (high capacitance in current and specific transconductance), due to the reduced gate oxide thickness, the polysilicon shield can introduce undesired effects of almost saturation due to the strong modulation of the drain drift region and it can be inefficient in reducing the electrical fields. In particular, for solving these drawbacks U.S. Pat. No. 6,172,400 provides the use of more complex and expensive structures with thicker “bump oxide” below the shield gate electrode.
Moreover, by using this kind of polysilicon shield, which takes substantially “coplanar” conformation, it is necessary to consider the limits it imposes on the smaller device sizes which can be realized (and thus also on its series resistance), due to the simultaneous lithographic limits of width and separation between the two polysilicon layers forming respectively the gate electrode and the shield itself. Moreover, the complications should be considered which can derive from the self-aligned silicidification process of the active area layers, and i.e., of all the substrate portions which are not covered by a field oxide layer, which is frequently used in the platforms VLSI CMOS.
In fact, to obtain VLSI CMOS structures with high density and with high performance, the manufacturing processes of such devices are characterised by the following steps:                formation of gate oxide layers having reduced thickness,        reduced sizes of the device,        self-aligned silicidification of polysilicon layers and active areas,        planarization of the premetal and intermetal dielectric layers,        “plug” (in general of tungsten) as contacts on the silicon and polysilicon and as path between the different metalization layers.        
However, such standard process steps are not easily compatible with the process steps to realize the previously described discrete power devices.